The present invention relates to a process for forming coffers in integrated circuits and integrated structures incorporating such coffers. It applies more particularly to bipolar integrated circuits in which the thickness of the epitaxial layer is of the order of a few microns only.
Generally, in the technique of bipolar integrated circuits, each elementary component of the integrated circuit is formed inside a coffer for ensuring operation of this component independently of the phenomena which may occur in the zones corresponding to the adjacent components.
FIG. 1 shows a bipolar integrated circuit coffer obtained conventionally. This coffer is formed on a semiconductor substrate, generally of silicon designated by reference 1. It is defined laterally by a P.sup.+ type zone 2 having a closed contour, generally square or rectangular in shape. Between the lower part of the coffer and substrate 1 there is frequently formed a buried layer 3 of the same type of conductivity as the coffer, and of the opposite type of conductivity to that of the substrate, for example of type N.sup.+ if the substrate is of type P and the coffer of type N.
Conventionally this coffer, of type N, is formed by implanting initially in substrate P, substantially at the positions of the layer intended to become the buried layer 3, high-concentration doping impurities, then by growing an epitaxial layer 4 on the substrate and finally by effecting through an appropriate mask a diffusion so as to form the isolating walls 2 of the coffer.
One of the technological difficulties which arises during production of the coffers described above with reference to FIG. 1, resides in the fact that, once the buried layer 3 has been formed, then the epitaxial layer 4 has been caused to grow, the positions of the buried layer 3 cannot be "seen" from the upper surface of the substrate. It is then very difficult to position the mask for locating the diffusion of the insulating walls so as to align it with the mask which served for forming the buried layer 3.
Different processes have already been thought up in the prior art to try and resolve this problem.
One of the known processes consists, as is shown in FIG. 2, in etching in an oxide layer 10 formed at the surface of substrate 1 openings 11 in which the buried layers 12 of type N.sup.+ will be implanted. In a second stage shown in FIG. 3, a heat treatment is carried out at high temperature in a slightly oxidizing atmosphere. During this operation, the more rapid growth of the silica layer at the level of the visible silicon of the buried layer causes a depression in the surface of the silicon above this buried layer. This difference of level causes a step 13 to appear which delimits the periphery of the buried layer. Since the orientation of this step is different from the rest of the surface of the substrate and since the epitaxial growth is anisotropic, the growth of the silicon will occur obliquely with respect to the step.
There will then be obtained at the surface of the epitaxied layer, as shown in FIG. 4, an image of the depression which will not be straight above the one formed in the substrate. Furthermore, since the crystalline orientation of the facing facets is different, the displacements d.sub.1 and d.sub.2 which they will undergo will also be different and the image of the depression at the surface will be not only displaced but further deformed.
Although it is possible, in strictly controlled conditions of epitaxial growth to obtain reproducible displacements and deformations, it appears that this method does not allow great accuracy to be obtained in the alignment of the etching which will define the insulating walls with respect to the underlying buried layer. Practically, by taking into account the constant displacement for given conditions of growth, it is not possible to ensure this alignment with an accuracy greater than 1.mu. and this for epitaxied layers not exceeding 3.mu. in thickness.
Another process of the prior art for positioning the insulating mask with respect to the buried layer consists in taking a reference point on the rear face of the substrate. This reference point formed during etching of the buried layer requires an optical polished rear face so that its geometrical definition is sufficient during alignment. But with the methods used, the accuracy is not even as good as before and is all the more poor that the wafer is thick, which limits its use to wafers of small diameter or to power devices in which the alignment is not very critical.